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Data Sheet
ADuM1210
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
4.5 V ≤ V DD1 ≤ 5.5 V, 4.5 V ≤ V DD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range,
unless otherwise noted. All typical specifications are at T A = 25°C, V DD1 = V DD2 = 5 V. All voltages are relative to their respective ground.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel,
I DDI (Q)
0.50
0.60
mA
Quiescent
Output Supply Current, per Channel,
I DDO (Q)
0.19
0.25
mA
Quiescent
Total Supply Current, Two Channels 1
DC to 2 Mbps
V DD1 Supply Current
V DD2 Supply Current
I DD1 (Q)
I DD2 (Q)
1.1
0.5
1.4
0.8
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
10 Mbps
V DD1 Supply Current
V DD2 Supply Current
I DD1 (10)
I DD2 (10)
4.3
1.3
5.5
2.0
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
Input Currents
I IA , I IB
?10
+0.01
+10
μA
0 V ≤ V IA , V IB ≤ V DD1
Logic High Input Threshold
Logic Low Input Threshold
V IH
V IL
0.7 × V DD1
0.3 × V DD1
V
V
Logic High Output Voltages
V OAH , V OBH
V DD2 ? 0.1
V DD2 ? 0.5
5.0
4.8
V
V
I Ox = ?20 μA, V Ix = V IxH
I Ox = ?4 mA, V Ix = V IxH
Logic Low Output Voltages
V OAL , V OBL
0.0
0.04
0.2
0.1
0.1
0.4
V
V
V
I Ox = 20 μA, V Ix = V IxL
I Ox = 400 μA, V Ix = V IxL
I Ox = 4 mA, V Ix = V IxL
SWITCHING SPECIFICATIONS
Minimum Pulse Width 2
Maximum Data Rate 3
PW
10
100
ns
Mbps
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Propagation Delay 4
Pulse Width Distortion, |t PLH ? t PHL | 4
Change vs. Temperature
Propagation Delay Skew 5
Channel-to-Channel Matching,
t PHL , t PLH
PWD
t PSK
t PSKCD
20
5
50
3
15
3
ns
ns
ps/°C
ns
ns
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Codirectional Channels 6
Channel-to-Channel Matching,
t PSKOD
15
ns
C L = 15 pF, CMOS signal levels
Opposing-Directional Channels 6
Output Rise/Fall Time (10% to 90%)
t R /t F
2.5
ns
C L = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
|CM H |
25
35
kV/μs
V Ix = V DD1 , V CM = 1000 V,
at Logic High Output 7
transient magnitude = 800 V
Common-Mode Transient Immunity
|CM L |
25
35
kV/μs
V Ix = 0 V, V CM = 1000 V,
at Logic Low Output 7
transient magnitude = 800 V
Refresh Rate
Input Dynamic Supply Current,
f r
I DDI (D)
1.2
0.19
Mbps
mA/Mbps
per Channel 8
Output Dynamic Supply Current,
I DDO (D)
0.05
mA/Mbps
per Channel 8
1
2
3
Supply current values are for both channels running at identical data rates. Output supply current values are specified with no output load present. The supply current
associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total V DD1 and V DD2 supply
currents as a function of data rate.
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
Rev. D | Page 3 of 20
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